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    • 专利摘要:
    The present invention relates to a method for forming an electronic device intended to accommodate at least one completely deserted FDSOI type transistor and at least one PDSOI partially deserted transistor, from a stack of layers (10) comprising at least an insulating layer (100) surmounted by at least one active layer (200) of a semiconductor material, the method comprising at least one dry etching step and a step of height adjustment between at least two etched elements.
    公开号:FR3051973A1
    申请号:FR1654651
    申请日:2016-05-24
    公开日:2017-12-01
    发明作者:Pascal Costaganna；Francis Domart；Gregory U'ren
    申请人:Altis Semiconductor SNC；
    IPC主号:
    专利说明:

    TECHNICAL FIELD OF THE INVENTION
    The present invention relates to the field of microelectronics and nanoelectronics and more particularly the field of partially deserted transistors and completely deserted transistors mounted on the same semiconductor wafer.
    STATE OF THE ART
    In the field of integrated circuits formed from elaborate semi-conductor-on-insulator substrates, designated by their acronym SOI, of the English "Semiconductor On Insulator", there are generally two types of transistors used: Partially deserted transistors designated by their acronym PDSOI, of the English Partially Depleted Semiconductor On Insulator, and so-called completely deserted transistors designated by their acronym FDSOI, of the English "Fully Depleted Semiconductor On Insulator".
    An SOI-developed substrate is characterized by the presence of a thin surface layer of monocrystalline semiconductor, monocrystalline silicon for example, resting on a continuous insulating layer of oxide, for example silicon oxide, called buried oxide or BOX stands for "Buried Oxide Layer". The solidity and the mechanical rigidity of the assembly are ensured by a layer on which the BOX rests and which constitutes the body of the SOI substrate, often qualified of the English word of "bulk" to indicate that the starting substrate is very generally made of a solid semiconductor material, silicon for example. This structure offers many advantages for the realization of MOS transistors, the acronym for "Metal-Oxide Semiconductor". In particular, it allows a drastic reduction of parasitic capacitances due to the presence of the insulating continuous layer.
    Both types of transistors FDSOI and PDSOI meet specific needs in the field of analog and digital electronics, and more particularly in the field of radio frequency electronics.
    It is thus known from the prior art electronic devices comprising FDSOI transistors and PDSOI transistors on the same electronic chips. The prior art then has several training solutions of this type of electronic devices. However solutions are relatively complex and expensive to implement in order to reproducibly obtain on the same chip transistors whose performance is high. There is therefore a real need to simplify the manufacture and reduce the production costs of this type of electronic devices.
    SUMMARY OF THE INVENTION
    The present invention relates to a method of forming an electronic device intended to accommodate at least one totally deserted transistor (FDSOI) and at least one partially deserted transistor (PDSOI), from a stack of layers comprising at least one insulating layer. surmounted by at least one active layer made of a semiconductor material, the method comprising at least the following steps: - forming at least one insulating trench through the thickness of the active layer to define in said active layer, from and else of the insulating trench, at least a first active region on which is intended to be formed at least one partially deserted transistor (PDSOI) and at least a second active region on which is intended to be formed at least one totally deserted transistor (FDSOI); - forming, above the at least one first active region and on a portion of the insulating trench, a masking layer without covering the at least one second active region and without covering a portion of the insulating trench; Simultaneously etching by dry etching so as to form etched areas: part of the thickness of the active layer of the at least one second active region so as to form at least one second thinned active region and to obtain; in the at least one second thinned active region, a thickness of the active layer lower than in the at least one first active region; ο at least a portion of the thickness of the uncoated portion of the insulating trench so as to form an etched portion of the insulating trench; O and the entire masking layer. - Adjust, after the dry etching step, the height of the surface of the at least one second active region thinned at the height of the surface of said etched portion of the insulating trench.
    The present invention makes it possible to form on the same semiconductor substrate, preferably of the SOI type, a plurality of partially deserted transistors of the PDSOI type and totally deserted transistors of the FDSOI type in a minimum of steps by the use of step-wise steps. both economic in terms of process time but also compared to the chemistries commonly used in the prior art. The present invention indeed benefits from a synergy of these steps in order to maximize the utility of each of them while minimizing their number.
    This synergy is based on two steps, namely a dry etching step and a step of forming a sacrificial oxide layer: the dry etching makes it possible to simultaneously etch a plurality of layers and different materials and the sacrificial oxide layer makes it possible to improve the performance of the FDSOI transistor while facilitating the formation of the source and drain zones by its screening effect during the subsequent ion implantation steps.
    Dry etching is a step for thinning quickly and simply a region of the active layer while thinning a portion of the insulating trenches surrounding said thinned region of the active layer.
    Advantageously, this dry etching step makes it possible to remove the masking layer, also called hard mask, from the PDSOI zones at the same time as it makes it possible to thin a region of the active layer and a portion of the insulating trenches. In order to be able to simultaneously etch three materials of different nature and this so that the desired thinning thickness corresponds to the complete etching of one of the three materials, preferably the masking layer, the choice of their nature and structure is a critical point, as is the choice of dry etching.
    Advantageously, an oxide, preferably silicon, formed by plasma-enhanced chemical vapor deposition said LPCVD oxide of the acronym "Low-Pressure Chemical Vapor Deposition" and an oxide, preferably silicon, formed by chemical deposition in vapor phase performed at sub-atmospheric pressure called PECVD oxide of the acronym "Plasma-enhanced Chemical vapor deposition" were cleverly chosen to satisfy this condition. The PECVD oxide forms the insulating trenches while the LPCVD oxide forms the masking layer. Thus, a single etching step thus makes it possible to etch three different materials under the desired thinning and shrinking conditions.
    This dry etching step, however, leads to the formation of gutters at the junction between the thinned region of the active layer and the etched portions of the insulating trenches. These gutters result directly from the nature of dry etching at the interface between two different materials and lead to the subsequent formation of polycrystalline material rails in the posterior steps of the formation of FDSOI transistors. This phenomenon of formation of gutters, called "Microtrenching" in English, is well known to those skilled in the art and thus dissuaded him from using a dry etching to thin the active layer and a part of the trenches insulating.
    Indeed, at first glance, these gutters suggest that the performance of FDSOI transistors will be reduced. However, during the development of the present invention, the effects of these gutters on the performance of the transistors could be controlled. Surprisingly, the step of adjusting the height of the surface of the at least one second thinned region active at the height of the surface of said etched portion of the insulating trench makes it possible to control the structure of these gutters such that so that they do not adversely affect the performance of the FDSOI transistors.
    Regarding the use of a sacrificial oxide layer, it provides at least three distinct functions in synergy with the problem of reducing the cost of manufacture and with the previous step of dry etching.
    Indeed, this sacrificial oxide layer makes it possible on the one hand to improve the surface state of the thinned active layer by eliminating the surface defects of the thinned region of the active layer induced by dry etching, and on the other hand to adjust the height of this thinned region of the active layer to the height of the surface of the etched portion of the insulating trench so as to eliminate the nuisances of the gutters and optimize the performance of the FDSOI transistor, while maintaining executable steps simply to obtain said transistor.
    The present invention also relates to an electronic device intended to accommodate at least one totally deserted FDSOI transistor and at least one PDSOI partially deserted transistor obtained by the method according to the present invention.
    BRIEF DESCRIPTION OF THE FIGURES
    The objects, objects, as well as the features and advantages of the invention will become more apparent from the detailed description of an embodiment of the latter which is illustrated by the following accompanying drawings, in which: FIG. an embodiment of the present invention, an SOI type substrate advantageously comprising a plurality of layers located on the surface of an SOI structure including a masking layer. It is preferably from this type of stack of layers that the present invention can be implemented. FIG. 2 illustrates, according to an embodiment of the present invention, a step of depositing a resin intended to mask the future PDSOI regions. FIG. 3 illustrates, according to an embodiment of the present invention, the removal of said plurality of layers at the level of the future FDSOI region. FIG. 4 illustrates, according to an embodiment of the present invention, a dry etching step after removing said resin. This dry etching step aims, among other things, to thin the layers not covered by said masking layer. FIG. 5 illustrates, according to an embodiment of the present invention, the state of the substrate after the dry etching step with the presence of a residual oxide layer and the presence of gutters. FIG. 6 illustrates, according to an embodiment of the present invention, a wet cleaning step configured to remove said residual oxide layer. FIG. 7 illustrates, according to an embodiment of the present invention, a step of forming a sacrificial oxide layer on the surface of the thinned active layer. FIG. 8 illustrates, according to an embodiment of the present invention, a step of adjusting the height of the sacrificial oxide layer at the height of the PECVD oxide layer. FIG. 9 illustrates, according to an embodiment of the present invention, a step of removing a nitride layer. FIG. 10 illustrates, according to an embodiment of the present invention, an ion implantation step in order to form zones of sources and drains. FIG. 11 illustrates, according to an embodiment of the present invention, an FDSOI transistor and two PDSOI transistors formed according to an exemplary implementation of the present invention.
    The accompanying drawings are given by way of example and are not limiting of the invention. These drawings are schematic representations and are not necessarily at the scale of the practical application. In particular, the relative thicknesses of the layers and substrates are not representative of reality.
    DETAILED DESCRIPTION OF THE INVENTION
    The term PDSOI transistor or more generally PDSOI device, a device built in an area whose thickness is greater than the maximum depletion layer (in English maximum depletion layer) Wd max ·
    The term FDSOI transistor or more generally FDSOI device, a device built in an area whose thickness is smaller than the maximum depletion layer Wd max · The thickness of this maximum depletion layer Wd max is given by the equation:
    Wd_max = (2 £ s £ o29f / qN a)
    With: - £ si: the relative dielectric constant of silicon; - £ o: the absolute dielectric constant of the vacuum; - φρ = (/ (Τ / (7) Ιη (Λ / Α / ηί) -; - k: the Boltzmann constant; - T: the temperature; - n I: the intrinsic concentration of silicon carriers; - q: the elementary electrical charge - Λ / α: the concentration of impurities.
    Which at room temperature (300 K) gives φρ = 0.0259 ln (/ V a / 1.5x10 ^ °)
    In what follows, the following terms mean: - "PDSOI zone", an area of the substrate intended to receive at least one PDSOI transistor and comprising an active layer and a part of the insulating trenches located on either side of the active layer considered . - "FDSOI zone", an area of the substrate for receiving at least one FDSOI transistor and comprising an active layer and a portion of the insulating trenches located on either side of the active layer considered. - "PDSOI active region", a region of the substrate comprising an active layer for forming at least one PDSOI transistor. "Active region FDSOI", a region of the substrate comprising an active layer intended for forming at least one FDSOI transistor. "PECVD oxide", an oxide formed by plasma-assisted chemical vapor deposition. "LPCVD oxide", an oxide formed by chemical vapor deposition carried out at subatmospheric pressure.
    It is specified that in the context of the present invention, the term "slice", "substrate" or "chip" or their equivalents is defined as a device advantageously comprising one or more layers of semiconductors and configured to receive the formation of semiconductor structures of transistors type for example.
    It is specified that in the context of the present invention, the term "SOI substrate", or its equivalents are defined as a substrate characterized by the presence of a surface layer of monocrystalline semiconductor, monocrystalline silicon for example, based on a continuous insulating layer of oxide, for example silicon oxide, called buried oxide or BOX acronym of "buried oxide layer". The strength and mechanical rigidity of the assembly are provided by a support layer, for example made of silicon.
    It is specified that, in the context of the present invention, the terms "over", "overcomes" or "underlying" or their equivalent do not necessarily mean "in contact with". For example, the deposition of a first layer on a second layer does not necessarily mean that the two layers are in direct contact with one another, but that means that the first layer at least partially covers the second layer. being either directly in contact with it or separated from it by another layer or other element.
    In the following description, the thicknesses are generally measured in directions perpendicular to the plane of the lower face of the layer to be etched or a substrate on which the lower layer is disposed. Thus, the thicknesses are generally taken in a vertical direction in the figures shown.
    In the following description, the term "same height" or its equivalents, the fact that two distinct surfaces are located in the same plane parallel to the substrate that is to say, relative to the figures of the non-limiting example , the fact that two distinct surfaces are located in the same horizontal plane.
    In what follows, the term "leveling", "height adjustment" or their equivalents, the fact of modifying the thickness of a layer so that its surface is located in the same plane as the surface another layer, typically the same horizontal plane relative to the figures of the non-limiting example.
    In the context of the present invention, the resin is an organic or organo-mineral material that can be shaped by exposure to an electron beam, photons or X-rays or mechanically.
    In what follows, the term "etching" means the partial or total removal of a given material.
    In what follows, the term "wet etching", an etching technique requiring the use of chemistry in a humid environment, generally by baths.
    In what follows, the term "dry etching", a technique of etching in a non-humid environment, and preferably by the use of a plasma.
    By "compliant" is meant a geometry of layers which has, with manufacturing tolerances, a constant thickness despite changes in the direction of the layers, for example at the vertical sides of some structures.
    The term "step" does not necessarily mean that the actions taken during a step are simultaneous or immediately successive. Some actions of a first step can be followed in particular actions related to a different step, and other actions of the first step can be repeated next. Thus, the term step does not necessarily mean unitary actions and inseparable in time and in the sequence of the phases of the process.
    The term "structure" of a material is understood to mean the spatial distribution of its elementary constituents from a crystallographic point of view. Thus two layers of the same material may be of the same nature but have crystalline structures different from each other.
    The term "nature" of a material, its chemical composition and / or its crystalline structure. Thus two layers may be of the same chemical composition but of a different nature from a crystallographic point of view.
    Before beginning a detailed review of embodiments of the invention, are set forth below optional features that may optionally be used in combination or alternatively: Advantageously, the isolation trench 110 comprises at least one oxide formed by Plasma assisted chemical vapor deposition, this oxide is hereinafter called PECVD oxide. Advantageously, the masking layer 330 comprises at least one oxide formed by chemical vapor deposition carried out at subatmospheric pressure, this oxide is hereinafter called LPCVD oxide. Advantageously, the PECVD oxide is a silicon oxide. Advantageously, the LPCVD oxide is a silicon oxide.
    The choice of the deposition conditions and the nature of the PECVD and LPCVD oxides determines their respective etching rate during the dry etching step 400. According to one embodiment of the present invention, the conditions for forming and etching these two oxides are configured so that the total etch time of the LPCVD oxide corresponds to the etching of the desired thickness of the PECVD oxide. Advantageously, the dry etching 400, the oxide 110 formed by plasma-enhanced chemical vapor deposition and the oxide 330 formed by chemical vapor deposition carried out at subatmospheric pressure are configured, in particular the thickness of these oxides and / or their selectivity to etching, so that the formation time of Tau at least one etched portion of the insulating trench 112 corresponds to the etching time of the entire thickness of the masking layer 330. Advantageously, the step of adjusting the height of the surface 221a of the at least one second thinned active region 220a at the height of the surface 113 of said etched portion of the insulating trench 112 comprises at least the following steps: O oxidation of at least a portion of the second thinned active region 220a so as to form a sacrificial oxide layer 225; O at least partial removal of the sacrificial oxide layer 225 so as to form a residual sacrificial oxide layer 230 and so that the surface 231 of the residual sacrificial oxide layer 230 is at the same height as the surface 113 of the uncoated portion of the etched insulating trench 112. Advantageously, the sacrificial oxide layer 225 is formed by an oxidation step on a part of the thickness of the at least one second thinned active region 220a. . According to one embodiment, the sacrificial oxide layer 225 has a thickness preferably between 2 nm and 20 nm, advantageously between 5 nm and 15 nm, and preferably equal to 7.5 nm. Advantageously, the sacrificial oxide layer 225 has a thickness of preferably between 6 nm and 8 nm, and advantageously equal to 5 nm. Advantageously, the residual sacrificial oxide layer 230 has a thickness preferably between 0 and 10 nm, advantageously between 2 nm and 7 nm, and preferably equal to 5 nm. Advantageously, the dry etching 400 is a plasma etching. Advantageously, the plasma is a high density plasma. Advantageously, the parameters of plasma dry etching are: ## EQU1 ## (breakthrough or breakthrough phase)
    TCP 500W source power;
    4mT pressure;
    Helium (He) pressure at the back of the slice (He Cooling) 8T; CF4 50 sccm (Standard Cubic Centimeter per Minute, flow rate in cubic centimeter per minute measured under standard temperature and pressure conditions);
    Polarization power (in English "bias") 50W; O 2® "^ ® phase (so-called silicon etching)
    TCP 600W source power;
    25mT pressure;
    Helium pressure on the back of the slice (He Cooling) 8T; CI2 125 sccm 02 19 sccm;
    Bias power 400W; O 3®® ^ ® phase (called final cleaning)
    1200W TCP source power;
    LOmT pressure;
    Helium pressure on the back of the slice (He Cooling) 8T;
    Argon (Ar) 120 sccm / 02 sccm / CF4 sccm;
    Polarization power (in English "bias") OW. Advantageously, the active layer 200 has an initial thickness of preferably between 100 nm and 200 nm, advantageously between 125 nm and 180 nm, and preferably equal to 140 nm. Advantageously, the first active region 210 has a thickness preferably between 100 nm and 200 nm, advantageously between 125 nm and 180 nm, and preferably equal to 140 nm. - Advantageously, the at least one second thinned active region 220a has a thickness preferably between 25 nm and 100 nm, preferably between 50 nm and 85 nm, and preferably equal to 70 nm. Advantageously, the dry etching step 400 is followed by a wet cleaning step of the surface of said etched areas. - Advantageously, the wet cleaning step of the surface of said etched areas is configured to remove residual materials from the dry etching step 400. - Advantageously, the residual materials are oxides of the semiconductor material. Advantageously, the insulating trench 110 is in contact with the insulating layer 100. Advantageously, the step of forming the masking layer 330 above at least the first active region 210 and at least a part of the insulating trench 110 is preceded by the formation of an intermediate oxide layer 310 on the first active region 210. Advantageously, the step of forming the intermediate oxide layer 310 on the first active region 210 is followed by the forming a nitride layer 320 above the intermediate oxide layer 310 so that the masking layer 330 is at least partly in contact with said nitride layer 320. According to one embodiment, the insulating layer 100 has a thickness of between 50 nm and 1000 nm, advantageously between 200 nm and 600 nm and preferably equal to 400 nm. Advantageously, the intermediate oxide layer 310 has a thickness of between 1 nm and 10 nm, and preferably between 2 nm and 7 nm, and preferably equal to 5 nm. Advantageously, the nitride layer 320 has a thickness of between 10 nm and 150 nm, and preferably between 50 nm and 100 nm, and preferably equal to 70 nm. According to one embodiment, the thickness of the STIs 110 is between 100 nm and 200 nm, advantageously between 125 nm and 180 nm, and preferably equal to 140 nm. Advantageously, the thickness of the masking layer 330 is between 20 nm and 100 nm, preferably between 35 nm and 65 nm, and advantageously equal to 42.5 nm. Advantageously, the conditions for forming this PECVD oxide are as follows: ## EQU1 ##
    SiH4 40 sccm, H21200 sccm
    High Frequency Power (13.56 MHz) 0 W
    Low frequency power (250 kHz) 3000W O 2 ^^^^ phase: Ο2ΊΊ sccm,
    SiH4 40 sccm, H21200 sccm
    High Frequency Power (13.56 MHz) 2450W
    Low frequency power (250 kHz) 2750W O phase: O2104 sccm,
    SiH4 55 sccm, H21200 sccm
    High Frequency Power (13.56 MHz) 3000W
    Low frequency power (250 kHz) 2750W - Advantageously, the formation conditions of this masking layer 330 by LPCVD are as follows: Temperature 650 ° C., pressure 250 mTorr, TEOS flow rate 100 CC / min. Advantageously, the wet cleaning step is carried out based on hydrofluoric acid of DHF / SCI / SC2 type and comprises the following parameters:
    O DHF18SC1 SC2surFSI O HF 170 cc / min + DI water hot 1700 cc / min 88 sec O SCI: H202 200 cc / min NH40H 125cc / min Water DI Hot 1500 cc / min 45sec O NH40H 40 cc / min Water Di Hot 1600 cc / min 180 sec O SC2: HCL 40 cc / min H202 = 200 cc / m. Water DI Hot 1600cc / mn
    An exemplary embodiment of the invention will now be detailed with reference to the figures.
    The present invention provides a method of manufacturing on the same SOI substrate 10 PDSOI transistors and FDSOI transistors. Such a substrate 10 comprises a thin surface layer of a monocrystalline semiconductor, advantageously monocrystalline silicon, called an active layer 200. This active layer 200 rests on an insulating layer 100. Preferably, this active layer 200 rests on a single layer. support layer, not shown.
    According to one embodiment, the result of which is illustrated in FIG. 1, from this SOI substrate, an intermediate oxide layer 310 is formed on the entire surface of the substrate. This intermediate oxide layer 310 preferably comprises silicon oxide.
    According to one embodiment, a nitride layer 320 is deposited on the entire intermediate oxide layer 310. This nitride layer 320 is advantageously formed by LPCVD. According to one embodiment, the chemical composition of this nitride layer is Si3N4.
    Once these two layers (310 and 320) have been formed, a series of lithography steps makes it possible to form insulating trenches 110 called STIs of their acronym "Shallow trench isolation" illustrated in FIG.
    Very advantageously, these STIs 110 are formed from a PECVD oxide, and preferably a silicon PECVD oxide.
    Preferably, the STIs 110 are in contact with the BOX 100 as illustrated in FIG.
    It is known to those skilled in the art many techniques for forming ITS. For the present invention, the criterion of the nature of the oxide is an important criterion. Indeed, this oxide is preferably a silicon oxide formed by PECVD.
    A possible mode of formation of these STIs 100 relies on the use of conventional lithography techniques to form trenches in the substrate 10. These trenches are then filled with an oxide, preferably a PECVD silicon oxide.
    On either side of these STIs 110, regions of the active layer 200 are defined. A first active region 210 is called PDSOI active region because it is intended to form PDSOI 700 transistors. A second active region 220 is called FDSOI active region because it is intended to form FDSOI transistors 600.
    Once these regions 210 and 220 defined by the formation of the STIs 110, a masking layer 330 is deposited preferably according to a conformal deposit to form the layer 330 illustrated in Figure 1.
    In a very advantageous manner, the masking layer 330 comprises an LPCVD oxide, and preferably an LPCVD silicon oxide. This masking layer 330 can also be called hard mask or "hard mask" in English.
    Once the masking layer 330 has been formed, we obtain a substrate as shown in FIG.
    Two zones illustrated in FIG. 2 are defined as follows: a PDSOI zone 201 comprising an active region PDSOI 210, that is to say an active layer 210 intended for the formation of at least one PDSOI transistor 700, and comprising a portion ST1110 located on either side of the active layer 210. O an FDSOI 202 area comprising an active region FDSOI 220, that is to say an active layer 220 for the formation of at least one FDSOI transistor 600 , and comprising a portion of the ST1110 located on either side of the active layer 220.
    Figure 2 also illustrates the deposition over the PDSOI areas of a protective layer 340, advantageously comprising a resin. This protective layer 340 is advantageously deposited on at least part of the surface 331 of the masking layer 330.
    According to a preferred embodiment, the protective layer 340 is deposited so as to cover part of the STIs 110, preferably substantially 50% of their surface. It is opened by one of the many known methods of lithography, for example photolithography if it is a photosensitive resin.
    FIG. 3 illustrates a step of etching the FDSOI zones so as to remove the masking layer 330, the nitride layer 320 and the intermediate oxide layer 310. This etching step is preferably carried out chemically on the basis of a Fluorocarbon chemistry for example. This etching, preferably wet, has the result of exposing the surface 221 of the FDSOI active region 220, as well as at least a portion of the surface of the STIs 110.
    FIG. 4 illustrates the dry etching step 400 configured to thin the FDSOI zone 202, and more particularly the active layer 220 and at least a portion of the STIs 110, the portion not covered by the masking layer 330.
    This dry etching step 400 is advantageously preceded by the removal of the protective layer 340. This removal can advantageously be performed using an oxygen plasma. This removal is preferably followed by wet cleaning to remove any residue from the protective layer 340.
    In addition, a cleaning of the native oxide present on the surface of the substrate can be advantageously carried out by a carbon tetrafluoride base chemistry. This cleaning then prepares the surfaces of the FDSOI 202 zone in the dry etching step 400. The dry etching step 400, performed by plasma, preferably by a high density plasma, aims to thin the FDSOI zone. This high density plasma is advantageously based on chlorine and oxygen based chemistry.
    According to one embodiment, the dry etching 400 by high density plasma is configured to achieve an etching rate of the order of 1 nm per second for the materials in question, and preferably for the active layer 220 advantageously composed of monocrystalline silicon.
    Preferably, this dry etching 400 is subject to a retroactive loop for measuring the etched thickness, advantageously by interferometry. Thus, the etching is performed by multiple successive etchings separated from an interferometric measurement of the consumed thickness of the materials considered and preferably of the active layer 220.
    Advantageously, this dry etching 400 is configured to thin the active layer 220 of the FDSOI region.
    Preferably, this dry etching 400 is configured to thin a portion of STI 110, portion belonging to the FDSOI region.
    Preferably, this dry etching 400 is configured to completely remove the masking layer 330, advantageously from the entire substrate 10.
    In a particularly clever way, this dry etching 400 is configured to simultaneously thin two materials of different nature and remove a third material. Said dry etching 400 is configured so that the total withdrawal time of the masking layer 330 corresponds to the etching time necessary for the desired thinning of the portions of the STIs 110 and the active layer 220.
    One of the advantages of this dry etching step 400 is the possibility of achieving an optimum thickness of the thinned active layer 220a of the order of 75 nm for the formation of FDSOI 600 transistors.
    This dry etching step 400 is particularly innovative because in a single step, the active layer 220 is thinned to reach the desired thickness for the formation of FDSOI 600 transistors, the masking layer 330 is removed from the PDSOI regions. and a portion of STIs 110, surrounding active layers 220, is thinned as well.
    This dry etching step 400 avoids the use of multiple chemical etchings which, in terms of both process time and cost, is not economical.
    The materials involved in this dry etching step 400 were selected and specifically formed to satisfy the relative etch rate conditions to obtain the result illustrated in FIG. 5.
    FIG. 5 illustrates the result of the dry etching 400 described above. The thinned active layer 220a and the etched portions of the STIs 112 have been formed at the same time as the total removal of the masking layer 330.
    As a consequence of this dry etching 400, a residual oxide layer 410 has been formed on all the etched surfaces, for example on the entire substrate 10. It is a residue of the etching step dry 400.
    We also note the formation of cavities 120, said gutters 120 by their geometric shape, the vertical interfaces between the active layer 220a and the etched parts of STI 112.
    This gutter phenomenon 120 is well known to those skilled in the art, it is traditionally observed at the vertical interfaces between two materials of different nature during a simultaneous etching of these two materials. This phenomenon is one of the reasons that would distract the skilled person from the present invention. Indeed, this structural discontinuity seems at first glance a defect affecting the performance of the FDSOI 600 transistors.
    However, during the development of the present invention, it has surprisingly been noted that these structural defects 120, that is to say these gutters 120, can be reduced and that they do not then present. no or few limitations on the performance of the FDSOI 600 transistors.
    Indeed, the gutters 120 are reduced by the adjustment of the various chemical etching processes. In fact, the depth of the gutters 120 in the FDSOI transistors areas is reduced and avoids the presence after polysilicon etching of the grid, polysilicon filaments source of parasitic connections between the different polysilicon lines of the FDSOI transistors.
    As will be presented hereinafter, these gutters 120 are filled with polycrystalline materials during the subsequent steps of forming the FDSOI 600 transistors and mainly the gate of said FDSOI 600 transistors.
    A wet cleaning step, illustrated in FIG. 6, follows the dry etching 400. This wet cleaning is configured to remove the residual oxide layer 410 from all of the surfaces under consideration.
    For example, this wet cleaning can be carried out based on hydrofluoric acid, preferably diluted.
    This wet cleaning is configured to expose at least one of the following surfaces: O surface 321 of the nitride layer 320; O the surface 221a of the thinned active layer 220a; O the surface of the gutters 120; O the surface of STIs 110.
    FIGS. 7 and 8 illustrate the step of adjusting the height of the surface 221a of the thinned active layer 220a at the height of the surface 113 of the etched portions of the STIs 112. This height adjustment then makes it possible, among other things, to to reduce the geometrical shape of the gutters 120 so that they do not have a limitation on the performance of the FDSOI transistors.
    Advantageously, the gutters 120 are reduced by the adjustment of the various chemical etching processes. In fact, the depth of the gutters in the areas of FDSOI transistors is reduced and avoids the presence after polysilicon etching of the grid, polysilicon filaments source parasitic connections between the different polysilicon lines of the FDSOI transistors.
    This height adjustment comprises at least two steps: the formation of a sacrificial oxide layer 225 and the removal of at least a portion of this sacrificial oxide layer 225.
    The formation and partial removal of a sacrificial oxide layer 225 act synergistically with the previous dry etch step 400 to reduce the cost of producing electronic devices.
    Firstly, this sacrificial oxide layer 225 makes it possible to improve the surface state of the thinned active layer 220a, that is to say to structurally clean the surface 221a. Indeed, the surface 221a results from a dry etching which can leave the surface 221a damaged at the crystallographic level on a very small thickness of the order of a few nanometers for example. Partial removal of this sacrificial oxide layer 225 then makes it possible to remove the damaged portion of the surface 221a leaving only a residual sacrificial oxide layer 230 whose surface 231 no longer has this structural damage.
    Then, the partial removal of the sacrificial oxide layer 225 allows the surface 231 of the residual sacrificial oxide layer 230 to be leveled with the height of the surfaces 113 of the engraved portions of the STIs 112. This upgrade then eliminates the limiting effects of the gutters 120 on the performance of the FDSOI 600 transistors.
    Finally, the residual sacrificial oxide layer 230 forms a screen with ion implantations subsequently made for the purpose of forming source areas (610, 710) and drains (620, 720). This screen ensures a better homogeneity of implantation by avoiding the effects of channeling and it also makes it possible to limit the structural damage due to the ionic implantations.
    Thus, a single height adjustment step makes it possible to restore a surface structure that is absent from defects, to eliminate the disadvantages resulting from the formation of gutters 120 and to allow future ion implantation.
    FIG. 9 illustrates a step of removing the nitride layer 320 at the PDSOI zones so as to expose the surface 311 of the intermediate oxide layer 310. This shrinkage can be carried out wet, for example, in order not to not to damage the surface 231.
    Figure 10 illustrates ion implantation step 500 to form source and drain zones.
    Advantageously, this ion implantation step 500 can comprise two sub-steps corresponding to a first ion implantation of the PDSOI zones followed by a second ion implantation of the FDSOI zones. This thus makes it possible to have several degrees of freedom in the choice of doses and implanted elements in order to meet the various needs in terms of characteristics of the PDSOI 700 and FDSOI 600 transistors.
    This ion implantation step 500 advantageously benefits from the presence of the intermediate oxide layer 310 at the PDSOI zones and the residual sacrificial oxide layer 231 at the FDSOI zones in order to ensure good homogeneity of implantation. and to limit the structural defects of ion implantation. The intermediate oxide layers 310 at the PDSOI and residual sacrificial oxide zones 231 at the FDSOI zones then act as a screen to optimize the formation of the sources and drains.
    FIG. 11 illustrates, according to one embodiment, an FDSOI transistor 600 formed above the thinned FDSOI active region 220a and two PDSOI 700 transistors, half-represented in FIG. 11, formed above the PDSOI active regions 210.
    In FIG. 11, each transistor is summarily illustrated. Each transistor comprises at least one source zone (610, 710) and one drain zone (620, 720), raised in this example, a gate (630, 730) preferably comprising a plurality of layers and potentially electrically insulating spacers. the flanks of each grid (630, 730) of the source areas (610, 710) and drains (620, 720).
    FIG. 11 illustrates the position of the PDSOI transistors 700 and the FDSOI transistors 600 with respect to the PDSOI 201 and the FDSOI 202 zones according to one embodiment of the present invention.
    The present invention relates to a method of manufacturing an electronic device capable of forming on the same silicon wafer PDSOI and FDSOI transistors. The present invention comprises steps that have been studied, developed and optimized to present a synergy between them so as to reduce the production costs of such a device while not sacrificing the performance of this type of electronic devices.
    Thus, some of the pluralities have multiple effects in order to reduce the total number of necessary steps. The invention is not limited to the previously described embodiments and extends to all the embodiments covered by the claims.
    REFERENCES
    10. Stack of layers, SOI substrate 100. Insulating layer, BOX, silicon oxide 110. Insulating trenches, STI (Shallow Trench Isolation) 111. Part covered with insulating trenches by masking layer 112. Engraved part of insulating trenches 113. Surface of the engraved part of the insulating trenches 120. Cavities, Gutters 200. Active layer;
    201. ZonePDSOI
    202. FDSOI zone 210. First active region, PDSOI active region, active layer 220. Second active region, FDSOI active region, active layer 220a. Second thinned active region, thinned FDSOI active region, thinned active layer 221. Surface of second active region 221a. Surface of second thinned active region 225. Sacrificial oxide layer 226. Surface of sacrificial oxide layer 230. Residual sacrificial oxide layer 231. Surface of residual sacrificial oxide layer 310. Intermediate oxide layer 311. Surface of the intermediate oxide layer 320. Nitride layer 321. Surface of the nitride layer 330. Masking layer 331. Surface of the masking layer 340. Protective layer, resin 400. Dry etching; 500. Ion implantation;
    600. Transistor completely deserted, FDSOI transistor 610. Source area 620. Drain area 630. Grid 700. Partially deserted transistor, PDSOI transistor 710. Source area 720. Drain area 730. Grid
    权利要求:
    Claims (15)
    [1" id="c-fr-0001]
    1. A method of forming an electronic device intended to accommodate at least one completely deserted transistor (FDSOI) (600) and at least one partially deserted transistor (PDSOI) (700), from a stack of layers (10) comprising at least one insulating layer (100) surmounted by at least one active layer (200) of a semiconductor material, the method comprising at least the following steps: forming at least one insulating trench (110) through the thickness of the active layer (200) to define in said active layer (200), on either side of the insulating trench (110), at least a first active region (210) on which at least one PDSOI transistor (700) and at least one second active region (220) on which at least one FDSOI transistor (600) is to be formed; forming, over the at least one first active region (210) and a portion of the insulating trench (110), a masking layer (330) without covering the at least one second active region (220) and without covering a portion of the insulating trench (110); simultaneously etching (400) with dry etching so as to form etched areas: O part of the thickness of the active layer (200) of the at least one second active region (220) so as to form at least one second thinned active region (220a) and obtaining in the at least one second thinned active region (220a) a thickness of the active layer (200) lower than in the at least one first active region (210), O at least part of the thickness of the uncoated portion of the insulating trench (110) so as to form an etched portion of the insulating trench (112), O and the entire masking layer (330), adjust, after the dry etching step (400), the height of the surface (221a) of the at least one second thinned active region (220a) at the height of the surface (113) of said etched portion of the insulating trench ( 112).
    [2" id="c-fr-0002]
    2. Method according to the preceding claim wherein the isolation trench (110) comprises at least one oxide formed by plasma-enhanced chemical vapor deposition.
    [3" id="c-fr-0003]
    3. Method according to any one of the preceding claims wherein the masking layer (330) comprises at least one oxide formed by chemical vapor deposition carried out at subatmospheric pressure.
    [4" id="c-fr-0004]
    4. Method according to the two preceding claims wherein the dry etching (400), the oxide (110) formed by plasma-enhanced chemical vapor deposition and the oxide (330) formed by chemical vapor deposition carried out under pressure sub-atmospheric are configured so that the formation time of the at least one etched portion of the insulating trench (112) corresponds to the etching time of the entire thickness of the masking layer (330).
    [5" id="c-fr-0005]
    A method according to any one of the preceding claims wherein the step of adjusting the height of the surface (221a) of the at least one second thinned active region (220a) to the height of the surface (113) said etched portion of the insulating trench (112) comprises at least the following steps: - oxidizing at least a portion of the second thinned active region (220a) so as to form a sacrificial oxide layer (225); partially removing the sacrificial oxide layer (225) so as to form a residual sacrificial oxide layer (230) and so that the surface (231) of the residual sacrificial oxide layer (230) is at the same height as the surface (113) of the etched portion of the insulating trench (112).
    [6" id="c-fr-0006]
    6. Method according to the preceding claim wherein the sacrificial oxide layer (225) is formed by an oxidation step on a portion of the thickness of the at least one second thinned active region (220a).
    [7" id="c-fr-0007]
    7. Method according to any one of the two preceding claims wherein the sacrificial oxide layer (225) has a thickness preferably between 6 nm and 8 nm, and advantageously equal to 5 nm.
    [8" id="c-fr-0008]
    The method of any one of the preceding claims wherein the dry etch (400) is a plasma etch.
    [9" id="c-fr-0009]
    9. Method according to the preceding claim wherein the plasma is a high density plasma.
    [10" id="c-fr-0010]
    10. Method according to any one of the preceding claims wherein the active layer (200) has an initial thickness preferably between 100nm and 200nm, preferably between 125nm and 180nm, and preferably equal to 140nm, and wherein the first active region (210) has a thickness preferably between 100nm and 200nm, advantageously between 125nm and 180nm, and preferably equal to 140nm, and wherein the at least one second thinned active region (220a) has a thickness of preferably between 25nm and lOOnm, advantageously between 50nm and 85nm, and preferably equal to 70nm.
    [11" id="c-fr-0011]
    The method of any one of the preceding claims wherein the dry etching step (400) is followed by a wet cleaning step of the surface of said etched areas.
    [12" id="c-fr-0012]
    12. Method according to the preceding claim wherein the wet cleaning step of the surface of said etched areas is configured to remove residual materials from the dry etching step (400).
    [13" id="c-fr-0013]
    The method of any of the preceding claims wherein the insulating trench (110) is in contact with the insulating layer (100).
    [14" id="c-fr-0014]
    The method of any one of the preceding claims wherein the step of forming the masking layer (330) over at least the first active region (210) and at least a portion of the isolating trench. (110) is preceded by the formation of an intermediate oxide layer (310) on the first active region (210).
    [15" id="c-fr-0015]
    15. The method according to the preceding claim wherein the step of forming the intermediate oxide layer (310) on the first active region (210) is followed by the formation of a nitride layer (320) above the intermediate oxide layer (310) so that the masking layer (330) is at least partly in contact with said nitride layer (320).
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    同族专利:
    公开号 | 公开日
    FR3051973B1|2018-10-19|
    EP3249689A1|2017-11-29|
    EP3249689B1|2021-03-17|
    US10181429B2|2019-01-15|
    US20170345724A1|2017-11-30|
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    法律状态:
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    2018-07-27| TP| Transmission of property|Owner name: X-FAB FRANCE, FR Effective date: 20180625 |
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    优先权:
    申请号 | 申请日 | 专利标题
    FR1654651A|FR3051973B1|2016-05-24|2016-05-24|PROCESS FOR FORMING TRANSISTORS PDSOI AND FDSOI ON THE SAME SUBSTRATE|
    FR1654651|2016-05-24|FR1654651A| FR3051973B1|2016-05-24|2016-05-24|PROCESS FOR FORMING TRANSISTORS PDSOI AND FDSOI ON THE SAME SUBSTRATE|
    EP17172067.5A| EP3249689B1|2016-05-24|2017-05-19|Method for forming pdsoi and fdsoi transistors on a single substrate|
    US15/602,362| US10181429B2|2016-05-24|2017-05-23|Method for the formation of transistors PDSO1 and FDSO1 on a same substrate|
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